1. Technical Field
The present invention relates to method and apparatus for reducing jitter or wander on internetworking between ATM network and PDH network, and more particularly relates to method and apparatus for reducing jitter or wander on internetworking between ATM network and PDH network interface by using a jitter absorber comprised of a First-In-First-Out (FIFO) buffer, and a clock smoother when recovering timing synchronization.
2. Related Art
Generally, ATM is a specific packet-oriented transfer mode using an asynchronous time division multiplexing technique where both line switching and packet switching are unified and many pieces of data information such as voice, video, and data are organized in fixed-sized packets, called cells each comprised of a data portion and a header portion for storing destination information needed to route the cell through the network at a constant bit rate. The operation of ATM networks is well known and so is the problem of jitter as disclosed, for example, in U.S. Pat. No. 5,287,347 for Arrangement For Bounding Jitter In A Priority-Based Switching System issued to Spanke, U.S. Pat. No. 5,274,680 for Device For The Transmission Of Synchronous Information By An Asynchronous Network, Notably An ATM Network issued to Sorton et al., U.S. Pat. No. 5,471,510 for Asynchronous Transfer Mode Digital Telecommunication Network Terminal Equipment Synchronization Device issued to Renault et al., U.S. Pat. No. 5,534,937 for Minimum-Delay Jitter Smoothing Device And Method For Packet Video Communications issued to Zhu et al., U.S. Pat. No. 5,563,884 for Reducing Multiplex Jitter In An ATM/MPEG System issued to Fimoff et al., and U.S. Pat. No. 5,640,388 for Method And Apparatus For Removing Jitter And Correcting Timestamps In A Packet Stream issued to Woodhead et al.
ATM network may be crossed connected with a plesiochronous digital hierarchy (PDH) network in the manner disclosed, for example, in U.S. Pat. No. 5,577,039 for System And Method Of Signal Transmission Within A Plesiochronous Digital Hierarchy unit Using ATM Adaptation Layers issued to Won et al., and assigned to the assignee of the instant application. A cross connection system for ATM and PDH data comprises a line interface unit, a multiplexer/demultiplexer, a plurality of ATM adaptation layer modules, a first stage cell multiplexer/demultiplexer, a second stage cell multiplexer/demultiplexer and a router. The ATM adaptation layer AAL1 performs a segmentation and reassembly (SAR) function. At the transmission side, the ATM adaptation layer AAL1 receives PDH digital signal level 3 (DS3) data and demultiplexes the same into 28 digital signal level 1 (DS1) data. ATM adaptation layer modules convert the 28 DS1 data to ATM cell streams. The ATM cell streams are multiplexed into a single ATM MUX cell stream and then multiplexed with another cell stream. A router receives the combined multiplexed cell stream adds a header field, and outputs an ATM cell. At the receiving side, the ATM cell data is converted back to DS3 PDH data using the same system components.
AAL1-SAR device is used to convert synchronous information of a PDH user into 4 bit synchronous information of an ATM cell stream for transmission via a network link. At the receiving side, the AAL1-SAR device extracts synchronous information for a PDH data stream in ATM cell streams and transmits the same to a timing recovery block for a transmission clock recovery. The timing recovery block recovers a transmission clock according to the DS1 (1.544 Mbps) and E1 (2.048 Mbps) line speed that includes delay jitter or wander. The jitter or wander represents a phase variation of a signal by noise and interference of a communication line, a variation of a circumference temperature or bit stuffing, etc. When the phase variation of a signal varies rapidly, jitter is generated. Likewise when the phase variation of a signal varies slowly, wander is generated. The jitter or wander can cause the loss of transmission data when reading data transmitted from a buffer or can cause a slip phenomenon wherein unreliable data is inserted among transmission data. However, in case that the timing recovery block generates a transmission clock having DS1 or E1 line speed, and the transmission clock includes a jitter or wander, such a jitter or wander can cause data error or false operation of overall network synchronization.